The present technique relates to an apparatus and method for handling write operations.
Data processing systems will often include multiple processing devices that can perform data processing operations on data, and those various processing devices may be arranged to have access to shared data in memory. Often the processing devices will include one or more levels of local cache in which the data manipulated by those processing devices may be cached to allow quicker access to that data than would be possible were the data required to be fetched from memory each time.
However, the presence of local caches can give rise to coherency issues where there is the potential for one processing device to access out-of-date data when the most up-to-date version is cached in another processing device's local cache.
Whilst hardware cache coherency mechanisms have been developed for such situations, those mechanisms can be relatively expensive to implement in terms of hardware area and/or execution time.